Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
There are many prior-art documents that provide different ways of designing non-planar ESD diodes. For example, US Patent documents U.S. Pat. No. 8,928,083B2. US2016/0020203A1. U.S. Pat. No. 7,560,784B2, US2014/0191319A1, US2006/0063334A1, U.S. Pat. No. 7,964,893B2, US2014/0183641A1, U.S. Pat. No. 9,006,054B2, US2014/0252476A1, U.S. Pat. No. 8,941,161B2, U.S. Pat. No. 9,177,951B2. U.S. Pat. No. 8,927,397B2, US2014/0217502A1, U.S. Pat. No. 9,368,629B, US2014/0131765A1, U.S. Pat. No. 9,391,060B2, US2015/0014809A1, U.S. Pat. No. 9,318,622B1, US2013/0292745A1. US2015/0091090A1, and U.S. Pat. No. 7,888,775B2 provide prior art ways of implementing BJT and SCR-like devices in FinFET technologies provide various designs of diode FinFET (non-planar ESD diodes), however, due to inefficacy of heat dissipation mechanisms and much higher packing density of active area (Fins/Nanowires), these designs exhibit an increased self-heating over the device active area, which leads to an early failure, hence lowered ESD robustness.
There are many prior-art documents that provide ways of implementing BJT and SCR-like devices in FinFET technologies such as but not limited to BJT/ggNMOS FinFET, SCR inventions in FinFET and bulk FinFET technology, SCR inventions with N and P trigger taps for injecting a trigger current (for tuning trigger/holding voltage) in planar SOI technology, and SCR inventions with N and P taps (terminals labeled with N-body and P-body) in a different scheme in order to control holding/trigger voltage in planar SOI technology. For example, US Patent documents US2010/0187656, US2015/0145592A1, US2007/0262386A1, US2007/0040221A1, US2015/0311342A1, US2012/0049282A1, US2013/0168732A1, US2013/0175578A1, US2013/0168771A1, U.S. Pat. No. 7,166,876B2, U.S. Pat. No. 9,214,540B2, US2016/0064371A1, US2015/0137255A1, US2004/0207021A1, U.S. Pat. No. 6,909,149B2, US2005/0212051 A1, US2009/0206367A1, U.S. Pat. No. 7,638,370B2, US2010/0207161A1, U.S. Pat. No. 9,240,471B2, U.S. Pat. Nos. 9,236,374B2, 7,135,745B, 8,963,201B2, and US2014/0097465A1 disclose prior art ways to implement BJT and SCR-like devices in FinFET technologies, however solutions provided in these prior-arts too suffer from high packing density and enhanced self-heating.
Although, the advent of non-planar technologies has paved new and efficient ways to replace their planar counterparts by offering beneficial technological solutions to scale conventional transistors, this has come with a price of lowered ESD robustness in these advanced technology nodes.
Encountered during operation, latch-up is characterized as a high current condition where the device is irreversibly latched into a single electrical state typically preventing the entire circuit from functioning properly and resulting in device damage, if not complete destruction. The latch-up condition is generally attributed to the presence and undesirable function of parasitic bipolar transistors inherently formed in the CMOS FET structure. Configuration of parasitic bipolar transistors is such that a closed loop feedback path typically has a gain that is greater than the one that exists. Thus, when random operational conditions such as electrical transients are encountered, regenerating feedback occurs with a resultant latch-up of the device's electrical state.
CMOS latch-up is a commonly recognized problem. Correspondingly, a large variety of methods of reducing parasitic loop gain have been proposed. These include, most notably, the provision of parasitic-current blocking or shorting guard-ring structures interposed between the complementary PMOS and NMOS FET transistors of the CMOS device, utilizing a deep peak or retrograde doping profile well region, irradiation of the CMOS device with high energy particles such as neutrons and protons, and provision of low resistivity buried layers in the CMOS structure. However, these methods are variously disadvantageous due to substantially increased device structure and fabrication process complexity, low degrees of reproducibility, excessive degradation of device's operating characteristics including substantially increased leakage currents, and, in particular, failure to reduce the parasitic feedback loop gain to less than one.
In principle, ESD robustness and latch-up immunity due to parasitic SCRs goes hand-in-hand. ESD is a random event that leads to massive flow of current (in amperes) between bodies having different electrostatic potential for sub-500 ns duration. Latch-up is a type of short circuit that can occur in an integrated circuit (IC). More specifically it is the inadvertent creation of a low-impedance path between power supply rails of a MOSFET circuit, triggering a parasitic structure that disrupts proper functioning of the part, possibly even leading to its destruction due to extremely high current. Typically, a technology offering efficient parasitic SCR device would have least immunity towards latch-up and vice-versa.
Further, it is also observed that a technology offering efficient parasitic SCR device for better ESD protection would have least immunity towards latch-up and vice-versa. Thus, from technology point of view, one would like to have efficient ESD SCR and BJT devices, and at the same time, one would like to ensure highest latch-up immunity of parasitic SCRs under the functional devices.
There is therefore a need in the art for a solution that ensures efficient ESD protection SCR and BJT devices and also possesses highest latch-up immunity of parasitic SCRs under the functional devices which can be across ESD protection devices in non-planar technologies, thereby enhancing product reliability and life expectancy. There is also a need to provide a solution that can selectively enhance parasitic (SCR/Bipolar) action in intended parasitic, ESD devices, whereas the same can suppress the parasitic (SCR/Bipolar) action in functional devices.
All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
In some embodiments, numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description used in the appended claims.